Integrated Circuits

PCB for converting SMD QFN-32 packages to through hole DIP-32 footprints. Solder the device to this PCB then attach pin headers (sold seperately) to connect to through hole footprints on PCBs, breadboards and IC sockets.

The AS3046 is Alfa’s version of the CA3046 IC in an SOIC package. The AS3046D consists of five general purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially-connected pair. The transistors are well suited to a wide variety of applications in low power systems. They may be used as discrete transistors in conventional circuits however, in addition, they provide the very significant inherent integrated circuit advantages of close electrical and thermal matching. The AS3046D is available in a 14-pin SOIC package. Features

• Matched pair of npn transistors
• VBE matched less than ±1 mV
• 5 general purpose monolithic transistors
• Wide operating current range

Applications

• Filters
• Custom designed differential amplifiers
• Temperature compensated amplifiers

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates. Features:

• Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings

CD4016B Series types are quad bilateral switches intended for the transmission or multiplexing of analog or digital signals. Each of the four independent bilateral switches has a single control signal input which simultaneously biases both the p and n device in a given switch on or off. Features:

• 20-V digital or ± 10-V peak-to-peak switching
• 280- typical on-state resistance for 15-V operation
• Switch on-state resistance matched to within 10 typ. over 15-V signal-input range
• High on/off output-voltage ratio: 65 dB typ. @ fis = 10 kHz, RL = 10 k
• High degree of linearity: <0.5% distortion typ. @ fis = 1 kHz, Vis = 5 Vp-p, VDD–VSS
• Extremely low off-state switch leakage resulting in very low offset current and high effective off-state resistance: 100pA typ.

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.

The SSI2130 offers unprecedented performance and features, but its ultra-compact QFN package can present prototyping challenges. The EVB2130 eases evaluation by providing a PCB that allows comprehensive exploration of capabilities. The EVB2130-P is fully populated and ready for the bench. With the exception of the SSI2130, all components are through-hole for easy construction and experimentation. A on-board +5V regulator and 2.5V reference simplify external power connections, and pots are provided for mixer control, PWM, and VCO setup. Switches ease selection of saw ramp direction plus Through-Zero and Pulse Modulation. Features

• PCB size: 108 x 82mm
• External Power: ±12V
• Inputs: Expo Freq 1V/Oct PWM In Aux 1 and 2 In FM In PM In Hard Sync Soft Sync
• Outputs: Sine Saw Triangle Pulse Square Mix Out

FXCore from Experimental Noize is a DSP designed for creating audio effects in pro-audio devices. FXCore can operate as a standalone device when paired with appropriate CODECs where it generates all necessary clocks or as part of a more complex system where it will lock to the word clock and bit clock provided by another part of the system.
FXCore can store up to 16 programs and their associated register preset values in its internal FLASH memory so no external program storage is required.

The AS3280 is Alfa’s version of the CA3280 IC in an SOIC package. The AS3280D consists of two variable operational amplifiers that are designed to substantially reduce the initial input offset voltage and the offset voltage variation with respect to changes in programming current. This design results in reduced "AGC thump," an objectionable characteristic of many AGC systems. Careful design of critical places of the circuit reduces the amplifier dependence upon thermal and processing variables.
The AS3280D has all the generic characteristics of an operational voltage amplifier except that the forward transfer characteristics is best described by transconductance rather than voltage gain, and the output is current, not voltage. The magnitude of the output current is equal to the product of transconductance and the input voltage.

This quad flip flop is a part used in our Relay True Bypass Switching Part 2: Momentary and Soft Touch Switches article. To read the full article and learn about a circuit for relay switching in stomp box effects, please see the following link. https://www.amplifiedparts.com/tech-articles/relay-true-bypass-switching-2 These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. Features:

• Standardized symmetrical output characteristics
• Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No.

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-Trigger Inputs
• Hysteresis Voltage (Typical):
  
  • 0.9 V at VDD = 5 V
  • 2.3 V at VDD = 10 V
  • 3.5 V at VDD = 15 V
• Noise Immunity Greater Than 50%
• No Limit On Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• For Quiescent Current at 20 V
• Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: 100 nA at 18 V and 25°C
• Low VDD and VSS Current During Slow Input Ramp
• 5-V, 10-V, and 15-V Parametric Ratings

CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Features:

• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

CD4024B is a 7-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low.

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. Features:

• Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No.

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:

• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
  
  • Exclusive-OR network (I)
  • Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: <1% (typ.) at VDD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod.

CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals. Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator.

The CD4050B devices are noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features:

• Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
• Package Temperature Range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V Parametric Ratings

Applications

• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters

The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B device consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off).

The CD4069UB device consists of six CMOS inverter circuits. These devices are intended for all general-purpose inverter applications where the medium-power TTL-drive and logic-level-conversion capabilities of circuits such as the CD4009 and CD4049 hex inverter and buffers are not required. Features:

• Standardized symmetrical output characteristics
• Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical)
• 100% Tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
• Meets all requirements of JEDEC tentative standard No. 13B, Standard Specifications for Description of B Series CMOS Devices

The CD4070B contains four independent Exclusive-OR gates. The CD4070B provides the system designer with a means for direct implementation of the Exclusive-OR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.

CD4071B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. Features:

• Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

The CD4077B contains four independent Exclusive-NOR gates. The CD4077B provides the system designer with a means for direct implementation of the Exclusive-NOR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.