Integrated Circuits

CMOS - CD4046, Micropower Phase-Locked Loop, 16-Pin DIP
CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:
  • Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
  • Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
  • Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
  • Choice of two phase comparators:
    • Exclusive-OR network (I)
    • Edge-controlled memory network with phase-pulse output for lock indication (II)
  • High VCO linearity: <1% (typ.) at VDD = 10 V
  • VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
  • Source-follower output of VCO control input (Demod.
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CMOS - CD4040, 12-Stage Ripple-Carry Binary Counter/Divider, 16-Pin DIP
The CD4040B is a 12-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.
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CMOS - CD4017, CMOS Decade Counter, 16-Pin DIP
CD4017B is a 5-stage Johnson counter having 10 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle.
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CMOS - CD4047, Low-Power Monostable/Astable Multivibrator, 14-Pin DIP
CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals. Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator.
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CMOS - CD4051, 8:1, 1-Channel Analog Multiplexer with Logic-Level Conversion, 16-Pin DIP
The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.
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CMOS - CD4029, Presettable Up/Down Counter, 16-Pin DIP
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low.
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CMOS - CD4094, 8-Stage Shift-and-Store Bus Register, 14-Pin DIP
CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high. Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast.
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CMOS - CD4021, 8-Stage Static Shift Register, 16-Pin DIP
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.
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