Integrated Circuits

The CD4069UB device consists of six CMOS inverter circuits. These devices are intended for all general-purpose inverter applications where the medium-power TTL-drive and logic-level-conversion capabilities of circuits such as the CD4009 and CD4049 hex inverter and buffers are not required. Features:

• Standardized symmetrical output characteristics
• Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical)
• 100% Tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
• Meets all requirements of JEDEC tentative standard No. 13B, Standard Specifications for Description of B Series CMOS Devices

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-Trigger Inputs
• Hysteresis Voltage (Typical):
  
  • 0.9 V at VDD = 5 V
  • 2.3 V at VDD = 10 V
  • 3.5 V at VDD = 15 V
• Noise Immunity Greater Than 50%
• No Limit On Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• For Quiescent Current at 20 V
• Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: 100 nA at 18 V and 25°C
• Low VDD and VSS Current During Slow Input Ramp
• 5-V, 10-V, and 15-V Parametric Ratings

The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse.

CD4016B Series types are quad bilateral switches intended for the transmission or multiplexing of analog or digital signals. Each of the four independent bilateral switches has a single control signal input which simultaneously biases both the p and n device in a given switch on or off. Features:

• 20-V digital or ± 10-V peak-to-peak switching
• 280- typical on-state resistance for 15-V operation
• Switch on-state resistance matched to within 10 typ. over 15-V signal-input range
• High on/off output-voltage ratio: 65 dB typ. @ fis = 10 kHz, RL = 10 k
• High degree of linearity: <0.5% distortion typ. @ fis = 1 kHz, Vis = 5 Vp-p, VDD–VSS
• Extremely low off-state switch leakage resulting in very low offset current and high effective off-state resistance: 100pA typ.

CD4024B is a 7-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.

CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-trigger action on each input with no external components
• Hysteresis voltage typically 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V
• Noise immunity greater than 50%
• No limit on input rise and fall times
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No.

The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B device consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off).

CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals. Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator.

CD4081B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features:

• Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Features:

• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high. Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast.

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates. Features:

• Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. Features:

• Standardized symmetrical output characteristics
• Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No.

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. Features:

• Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No.

The CD4070B contains four independent Exclusive-OR gates. The CD4070B provides the system designer with a means for direct implementation of the Exclusive-OR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.

CD4071B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. Features:

• Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

The CD4077B contains four independent Exclusive-NOR gates. The CD4077B provides the system designer with a means for direct implementation of the Exclusive-NOR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.